New Delhi:

MoS MeiTY, Rajeev Chandrashekhar launched the DIR-V program, in a bid to boost the start-up ecosystem.

Minister of State for Electronics and Information Technology, Rajeev Chandrashekhar, today launched Digital India RISC-V (DIR-V). The program is intended for next-generation microprocessors which are to be designed and manufactured by Start-Ups. The initiative will be a major boost for start-ups and will be instrumental in building a trillion-dollar Digital Economy.

As one of the concrete steps towards realizing the ambition of self-reliance and a momentous stride towards “Atmanirbhar Bharat”, Shri Rajeev Chandrasekhar announced today Digital India RISC-V Microprocessor (DIR-V) Program with an overall aim to enable creation of Microprocessors for the future in India, for the world and achieve industry-grade silicon & Design wins by December’2023.

While setting the aggressive milestones for commercial silicon of SHAKTI & VEGA and their design wins by December 2023, Shri Rajeev Chandrasekhar mentioned that DIR-V will see partnerships between Startups, Academia & Multinationals, to make India not only a RISC-V Talent Hub for the World but also supplier of RISC-V SoC (System on Chips) for Servers, Mobile devices, Automotive, IoT & Microcontrollers across the globe.

Reminiscing his early days as x-86 processor chip designer at Intel, Shri Rajeev Chandrasekhar mentioned that many new processor architectures have gone through an initial period of ferment characterized by waves of innovations. At some point, however, they all settled on a dominant design. ARM and x-86 are two such instruction set architectures- one of which is licensed and other is sold, where industry consolidated in earlier decades. However, RISC-V has emerged as a strong alternative to them in last decade, having no licensing encumbrances, enabling its adoption by one and all in semiconductor industry, at different complexity levels for various design purposes.
Challenging the status quo, RISC-V Instruction Set Architecture (ISA) is not only witnessing a quantum leap and unprecedented levels of processor innovation owing to its free and open nature but also pushing the Moore’s Law beyond its limits. Today, there is a thriving ecosystem of chip designers at academia, scientific societies and startups in the country, contending to gain the market share in RISC-V growing market. While India has certainly taken several early steps in processor design area, the time is felicitous now to advocate India’s strides in RISC-V global community and unveil the Digital India RISC-V Processor roadmap to the world.

India today announces its ambitious roadmap with Ministry of Electronics and IT planning to join the RISC-V International as Premiere Board Member to collaborate, contribute and advocate India’s expertise with other global RISC-V leaders.

Shri Rajeev Chandrasekhar while announcing the DIR-V Program with Prof. V. Kamakoti, Director, IIT Madras as Chief Architect and Shri S. Krishnakumar Rao as Program Manager. He also unveiled not only the Blueprint of the roadmap of design & implementation of the DIR-V Program with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC but also the strategic Roadmap for India’s Semiconductor Design & Innovation to catalyze the semiconductor ecosystem in the country.

RISC-V ISA, being available in Open-Source, Dr. Rajendra Kumar, Additional Secretary and Shri Arvind Kumar, Group Coordinator (R&D in Electronics), MeitY projected its growth potential and mentioned that RISC-V will pave the way for next decade of computing design and innovations and adoption in future-generation of processors.

Mr. Bob Brennan, VP, Intel Foundry Services, while speaking about the IFS (Intel Foundry Services) Innovation Fund announced by Intel to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem, appreciated the Indian RISC-V movement.

Prof. V. Kamakoti, while highlighting the Intel’s support for getting fabricated 22nm SHAKTI Chip at Intel foundry, mentioned that DIR-V Program will catalyze the design innovation in the country and will encourage the several domestic startups working in RISC-V domains like- micro architecture design, verification and security aspects.

Mr. Naveed Sherwani, Chairman, RapidSilicon was of the view that with India joining the RISC-V International, the Global Open Source Hardware revolution will get a new leap forward. Ms Calista Redmond, CEO, RISC-V International highlighted the profound technical collaboration in RISC-V community by IIT Madras, one of five honored RISC-V Development partners. She also congratulated C-DAC for designing a range of RISC-V processors and InCore Semiconductors for releasing the Open-Source RISC-V Core Verification tool.

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